Demultiplexer apparatus and communication apparatus using the same

ABSTRACT

A demultiplexer apparatus has a plurality of integrating circuits which operate in parallel. The plurality of integrating circuits receive in parallel an input time-series binary data. One of the plurality of integrating circuits in a current stage converts the input binary data into multi-value data in the current stage, and generates recovery data in the current stage based on the multi-value data and recovery data from one of the plurality of integrating circuits in a stage immediately or more previous to the current stage integrating circuit. The plurality of integrating circuits output the generated recovery data as parallel data to the input binary data. In this way, the demultiplexer apparatus which can read the input binary data with a frequency component exceeding a maximum operation frequency is provided.

TECHNICAL FIELD

[0001] The present invention relates to a demultiplexer apparatus and acommunication apparatus using the same.

BACKGROUND ART

[0002] In a conventional communication apparatus, a receiver uses ademultiplexer apparatus, and the demultiplexer apparatus uses ademultiplexer circuit DEMUX. FIG. 1 shows the circuit structure exampleof a conventional demultiplexer apparatus of a shift register type.Referring to FIG. 1, the conventional demultiplexer apparatus of theshift register type has D-type flip-flops 50 ₁ to 50 ₈ connected as acascade of a plurality of stages (8 stages in the example shown in FIG.1). A latching circuit 51 receives in parallel the outputs of the D-typeflip-flops 50 ₁ to 50 ₈. Data is shifted for each clock through theD-type flip-flops. Thus, the number of process bits per clock is one.Such a technique is disclosed in, for example, IEICE Trans. Electron,(Vol. E78-C, No.12, 1995, p.1746): conventional reference 1).

[0003]FIGS. 2A and 2B show the circuit structure example of aconventional demultiplexer apparatus of a tree type. Referring to FIG.2A, in the conventional demultiplexer apparatus of the tree type, 1:2demultiplexers DEMUX 60 (60 ₁ to 60 ₇) are hierarchically arranged. Asshown in FIG. 2B, the 1:2 demultiplexer DEMUX 60 ₁ at a first stagedefines an operational rate and alternately reads the data for theflip-flops in two systems. Thus, it can process the data of two bits foreach clock. Such a technique is disclosed in, for example, IEICE Trans.Electron, (Vol. E78-C, No.12, 1995, p1746: conventional reference 2).

[0004] Also, an over-sampling method is proposed in which one data isread a plurality of times. Such a technique is disclosed in, forexample, Symp. On VLSI Circuits Digest of Technical papers (1997, p.71:conventional reference 3).

[0005] In a method of using binary logic flip-flops in an input unit, inany case of the logics, the input section is operated as schematicallyshown in FIGS. 3A and 3B. In FIG. 3A, a switch SW1 is closed (turned on)in a former part of a one-clock period, and a switch SW2 is opened(turned off). An input data is sampled by a capacitor C. As shown inFIG. 3B, the switch SW1 is opened (turned off) in a latter part of theone-clock period, and the switch SW2 is closed (turned on). The dataheld by the capacitor C is sent to a flip-flop at a next stage (notshown).

[0006] If the frequency of the clock used for the sampling is themaximum operational frequency of a transistor to be used, in order tocarry out the accurate sampling, one sampling requires at least asampling time equal to half the clock period. In short, the data ratethat can be attained by this method is (the maximum operationalfrequency×2).

[0007] In the over-sampling method, as shown in FIGS. 4A to 4E, the data(DATA) is sampled the plurality of times at timings slightly differentfrom each other. That is, multi-phase clocks CLK0 to CLK3 are used tocarry out the sampling. The data is recovered from the plurality ofsample data by using a weighting function. In the example shown in FIGS.4A to 4E, the data is sampled at edges of a 4-phase clock, and 1 isrecovered as a recovery data (Decision Data) from 0111. Consequently, inthis case, the possible data rate is greater than (the maximumoperational frequency×2).

[0008] By the way, in FIGS. 4A to 4E, the waveform of the clocks CLK0 toCLK3 is illustrated as a rectangular wave. However, if a transistor isused such that the frequency of the clock is close to its maximumoperational frequency, the waveform of the clock becomes a sine wave.For this reason, the sample data contains an error because of theinfluence of the data before and after the data of a target to be read.This results in a problem that it is difficult to reduce an error rate.

[0009] In conjunction with the above-mentioned description, a signconverting circuit is disclosed in Japanese Laid Open Patent Application(JP-A P2000-165246). In the sign converting circuit for optical dualbinary transmission in this reference, a bit distributor receives a highspeed input signal and distributes this signal into low speed signalsinto N (N is an integer of 2 or more) systems. N sign converters areprovided for the distributed low signals of the N systems, and eachperform the sign conversion on the low speed signals, respectively. Abit synthesizer receives the low speed signals after the conversions ofthe N signs respectively outputted from the N sign converters, andlogically operates and synthesizes those respective low speed signals,and then generates a high speed output signals after the signconversions. Each of the sign converting circuits includes an EXORcircuit for generating an EXOR output of the corresponding low speedsignal and a delayed feedback signal one bit before.

DISCLOSURE OF INVENTION

[0010] Therefore, an object of the present invention is to provide ademultiplexer apparatus that can accurately read a serial data having afrequency exceeding a maximum operational frequency of a transistor tobe used and output a parallel data, and a communication apparatus usingthe same.

[0011] In an aspect of the present invention, the demultiplexerapparatus includes a plurality of integrating circuits that are operatedin parallel. The plurality of integrating circuits receive inputtime-series binary data commonly. Each of a current stage of theplurality of integrating circuits converts the input binary data intomulti-value data, and generates recovery data in the current stage inaccordance with the multi-value data and recovery data at a previousstage integrating circuit to the current stage integrating circuit. Theplurality of integrating circuits output the generated recovery data asparallel data to the input binary data.

[0012] Here, each of the plurality of integrating circuits generates therecovery data in the current stage in accordance with the convertedmulti-value data and the recovery data from the previous stageintegrating circuit, and outputs the generated recovery data to one ofthe plurality of integrating circuits in a next stage.

[0013] It is preferable that each of the plurality of integratingcircuits is operated at a timing shifted for one bit of the input binarydata from the previous stage integrating circuit.

[0014] Also, each of the plurality of integrating circuits has aconverting unit for converting the input binary data into themulti-value data for every predetermined bit quantity.

[0015] Also, the converting unit adds the input binary data n data by nbits (n is an integer of 1 or more) and generates the multi-value data.

[0016] Also, the converting unit has an adder, and the adder has acapacitor and a switch. The switch operates in response to a clocksignal to carry out the addition such that a charge is stored in thecapacitor and then the stored charge is discharged from the capacitorbased on the input binary data, or such that the charge is dischargedand then the capacitor is charged based on the input binary data. Atthis time, the adder may have a transfer gate connected to the capacitorand an output capacitor connected through the transfer gate to thecapacitor. It is preferable that the capacitance of the output capacitoris smaller than that of the capacitor. Also, it is preferable that thecapacitance of the capacitor is variable based on a period per each dataquantity of the input binary data.

[0017] Also, when a plurality of MOSFETs are provided to connect theirgate electrodes in parallel, the capacitance of the capacitor may beadjusted by forming or extinguishing a gate channel of each of theplurality of MOSFETs based on a period per data in the input binarydata.

[0018] Preferably, the waveform of the clock signal is determined suchthat current values with regard to the capacitor in first and finalportions in the addition are smaller than a current value during aperiod between the first and final portions in the addition.

[0019] Also, preferably, each of the plurality of integrating circuitsfurther has a plurality of comparing circuits for converting themulti-value data into a set of binary data, and different thresholds areallocated to the plurality of comparing circuits.

[0020] Each of the plurality of integrating circuits may further have arecovering unit for generating the recovery data in the current stage inaccordance with the set of the binary data and the recovery data from aprevious stage integrating circuit.

[0021] Also, each of the plurality of integrating circuits may include aplurality of recovering circuits provided for recovery data estimationsfrom the integrating circuit in the previous stage, and a selectingcircuit for selecting and outputting one of the recovery data estimationfrom the plurality of recovery data, on the basis of the recovery dataat the previous stage, as the recovery data at the current stage. Here,each of the plurality of recovering circuits generates the recovery dataestimation on the basis of the set of binary data and a correspondingone of the recovery data estimations.

[0022] Also, each of the plurality of integrating circuits may include aplurality of recovering circuits, a first switch for sequentiallyselecting one of the plurality of recovering circuits and sending theset of binary data to the selected recovering circuit, and a secondswitch for selecting one of the plurality of recovering circuits andoutputting the recovery data in the current stage from the selectedrecovering circuit. Each of the plurality of recovering circuitsgenerates the recovery data in the current stage on the basis of the setof the binary data and the recovery data of the integrating circuit at aprevious stage.

[0023] Preferably, each of the plurality of integrating circuits has alatching circuit for adjusting timings such that the generated recoverydata are simultaneously outputted as the parallel data to the inputbinary data.

[0024] Also, the demultiplexer apparatus may have a plurality ofintegrating circuits, and each of the plurality of integrating circuitsmay have the plurality of integrating circuits.

[0025] Also, the demultiplexer apparatus may include a plurality ofintegrating units and a selector for selecting one of the plurality ofintegrating units and outputting an output data from the selectedintegrating circuit as the parallel data. Here, each of the plurality ofintegrating units has the above plurality of integrating circuits. Atthis time, each of the plurality of integrating circuits may have alatching circuit for adjusting timings such that the generated recoverydata are simultaneously outputted as the parallel data to the inputbinary data.

[0026] Also, each of the plurality of integrating circuits may have afirst converting unit for generating a first multi-value data from theinput binary data for each data of a predetermined number and a secondconverting unit for generating a second multi-value data from the inputbinary data for each data of the predetermined quantity. The multi-valuedata contains the first multi-value data and the second multi-valuedata, and the second multi-value data contains data of a polarityopposite to that of the first multi-value data. At this time, each ofthe first and second converting units adds the input binary data by ndata (n is an integer of 1 or more) and generates the multi-value data.

[0027] Also, each of the first and second converting units may have anadder, and the adding circuit may have a capacitor and a switch. Theswitch operates in response to a clock signal to carry out the additionsuch a charge is stored in the capacitor and then the stored charge isdischarged from the capacitor based on the input binary data, or suchthat the stored charge is discharged, and then the capacitor is chargedbased on the input binary data. At this time, the adding circuit mayhave a transfer gate connected to the capacitor and an output capacitorconnected through the transfer gate to the capacitor. Preferably, acapacitance of the output capacitor is smaller than that of thecapacitor.

[0028] Also, it is preferable that the capacitance of the capacitor isvariable based on a period per data of the input binary data. At thistime, the capacitance of the capacitor may be adjusted, when a pluralityof MOSFETs are provided to connect their gate electrodes in parallel, achannel of each of the plurality of MOSFETs is formed or extinguished onthe basis of the period per data in the input binary data.

[0029] Also, preferably, the waveform of the clock signal is determinedsuch that current values through the stored charge at the first andfinal portions in the addition are smaller than that in a period betweenthe first and final portions in the addition.

[0030] Also, preferably, each of the plurality of integrating circuitsmay be provided for the fist and second converting units and furtherhave a plurality of comparing circuits for converting the multi-valuedata into sets of binary data. In this case, preferably, the samethresholds are allocated to the plurality of comparing circuits. Each ofthe plurality of integrating circuits may further have a recovering unitfor generating a recovery data in the current stage in accordance withthe set of the binary data and the recovery data from a previous stageintegrating circuit.

[0031] Also, each of the plurality of integrating circuits may have alatching circuit for adjusting the timings such that the generatedrecovery data are simultaneously outputted as the parallel data to theinput binary data.

[0032] Preferably, a communication apparatus includes any of theabove-mentioned demultiplexer apparatuses.

[0033] In another aspect of the present invention, the demultiplexerapparatus includes first to N-th integrating circuits (N is an integerof two or more) operating in parallel, which commonly receive a serialbinary data. The first to N-th integrating circuits are operated inresponse to first to N-th clock signals whose phases are different fromone another. Each of the integrating circuits refers to an output of theintegrating circuit at a previous stage, and the integrating circuit atthe first stage refers to an output of the N-th integrating circuit.Each of the integrating circuits includes an adding circuit for addingthe serial binary data for a plurality of bits, a comparing circuit forcomparing a multi-value data obtained by the addition through the addingcircuit with a reference voltage and then generating a plurality ofbinary data, and a recovering unit for recovering a parallel binary datafrom the plurality of binary data outputted from the comparing circuitsand the output result of the integrating circuit at the previous stage,and outputs at least a part of the recovered parallel binary data to theintegrating circuit at a next stage.

[0034] Also, the adding circuit has a first conductive type of a firstMOS transistor, a second conductive type of a second MOS transistor andthe second conductive type of a third MOS transistor which are connectedin series between a high potential side power supply and a low potentialside power supply. A clock signal to be sent to the integrating circuitis supplied to gates of the first MOS transistor and the third MOStransistor, and the serial binary data is inputted to a gate of thesecond MOS transistor. The adding circuit is further composed of a firstcapacitor, in which one end is connected to a connection point betweendrains of the first MOS transistor and the second MOS transistor, theother end is connected to the low or high potential side power supply,and a capacitance is variable, a transfer switch, which is connectedbetween the one end of the first capacitor and the output end of theadding circuit and controlled so as to be turned on and off by the clocksignal, and a second capacitor in which one end is connected to aconnection point between the transfer switch and the output end, and theother end is connected to the low or high potential side power supply. Acapacitance of the second capacitor is smaller than a capacitance of thefirst capacitor. At this time, when the third MOS transistor whose gatereceives the clock signal is in an on state, the transfer switch is inthe on state. When the third MOS transistor is at an off state, thetransfer switch is at the off state.

[0035] Also, when the adding operation using the first capacity isended, the transfer switch is turned off, and the second capacity isseparated from the first capacity. After that, the first capacity isdischarged or charged, and then returned to the state before the addingoperation. At a start of a next adding operation, the transfer switch isturned on, and the second capacity and the first capacity are set at thesame voltage.

[0036] Also, the integrating circuit may further include a latchingcircuit for receiving the output from the recovering unit, adjusting thetiming and outputting as the output data.

[0037] Preferably, the clock signal sent to the integrating circuit hasits phase which is delayed for one bit, as compared with the clocksignal sent to the integrating circuit at the previous stage.

[0038] Also, preferably, the recovering unit has a circuit forrecovering even-numbered bits and a circuit for recovering odd-numberedbits.

[0039] Moreover, preferably, the communication apparatus includes any ofthe above-mentioned demultiplexer apparatuses.

BRIEF DESCRIPTION OF DRAWINGS

[0040]FIG. 1 is a diagram showing the circuit structure of aconventional demultiplexer apparatus of a shift register type;

[0041]FIGS. 2A and 2B are diagrams showing the circuit structure of aconventional demultiplexer apparatus of a tree type;

[0042]FIGS. 3A and 3B are diagrams showing an operation of aconventional demultiplexer apparatus;

[0043]FIGS. 4A to 4E are diagrams showing an operational principle of aconventional demultiplexer apparatus of an over-sample method;

[0044]FIG. 5 is a diagram showing an operational principle of ademultiplexer apparatus of the present invention;

[0045]FIG. 6 is a block diagram showing the circuit structure of ademultiplexer apparatus according to a first embodiment of the presentinvention;

[0046]FIGS. 7A to 7D are timing charts showing an example of an inputclock signal used in the demultiplexer apparatus according to the firstembodiment of the present invention;

[0047]FIG. 8 is a block diagram showing the circuit structure of anintegrating circuit used in the demultiplexer apparatus according to thefirst embodiment of the present invention;

[0048]FIGS. 9A to 9J are timing charts showing an operation of theintegrating circuit used in the demultiplexer apparatus according to thefirst embodiment of the present invention;

[0049]FIG. 10 is a circuit diagram showing the circuit structure of anadding circuit in the integrating circuit of the demultiplexer apparatusin the first embodiment;

[0050]FIG. 11 is a circuit diagram showing the circuit structure of avariable capacitor of the adding circuit in the integrating circuit ofthe demultiplexer apparatus in the first embodiment;

[0051]FIGS. 12A to 12C are timing charts showing an operation of theadding circuit in the integrating circuit of the demultiplexer apparatusin the first embodiment;

[0052]FIGS. 13A and 13B are circuit diagrams showing the circuitstructure of a comparing circuit in the integrating circuit of thedemultiplexer apparatus in the first embodiment;

[0053]FIGS. 14A and 14B are circuit diagrams showing the circuitstructure of a recovering circuit in the integrating circuit of thedemultiplexer apparatus in the first embodiment;

[0054]FIG. 15 is a circuit diagram showing another example of thecircuit structure of the recovering circuit in the integrating circuitof the demultiplexer apparatus in the first embodiment;

[0055]FIG. 16 is a block diagram showing the circuit structure of anintegrating circuit of a demultiplexer apparatus according to a secondembodiment of the present invention;

[0056]FIG. 17 is a block diagram showing the circuit structure of arecovering circuit in the integrating circuit of the demultiplexerapparatus according to the second embodiment of the present invention;

[0057]FIG. 18 is a block diagram showing the circuit structure of arecovering circuit in an integrating circuit of the demultiplexerapparatus according to a third embodiment of the present invention;

[0058]FIG. 19 is a block diagram showing the circuit structure of arecovering circuit in an integrating circuit of the demultiplexerapparatus according to a fourth embodiment of the present invention;

[0059]FIG. 20 is a block diagram showing the circuit structure of anintegrating circuit of the demultiplexer apparatus according to a fifthembodiment of the present invention;

[0060]FIG. 21 is a block diagram showing the circuit structure of anintegrating circuit of the demultiplexer apparatus according to a sixthembodiment of the present invention;

[0061]FIGS. 22A to 22D are timing charts showing an operation of theintegrating circuit of the demultiplexer apparatus according to thesixth embodiment of the present invention;

[0062]FIG. 23 is a block diagram showing the circuit structure of anintegrating circuit of the demultiplexer apparatus according to aseventh embodiment of the present invention;

[0063]FIG. 24 is a block diagram showing the circuit structure of acommunication apparatus to which the demultiplexer apparatus of thepresent invention is applied; and

[0064]FIG. 25 is a diagram showing an operational principle of thedemultiplexer apparatus of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0065] Hereinafter, a demultiplexer apparatus of the present inventionand a communication apparatus using the same will be described in detailwith reference to the attached drawings.

[0066] In the communication apparatus using the demultiplexer apparatusof the present invention, as shown in FIG. 24, a low data rate paralleldata is converted into a high data rate serial data by a multiplexerapparatus (MUX). The converted serial data as an electric signal istransmitted to a remote portion, as they are. Or, as shown in FIG. 24,the electric signal is converted into an optical signal by a laser andthen transmitted. In a receiving circuit, the optical signal isconverted into an electric signal by an optical receiving circuit andreturned to the low data rate parallel data by a demultiplexer apparatus(DEMUX). In such a communication apparatus, a receiving section uses thedemultiplexer apparatus (DEMUX) of the present invention.

[0067]FIG. 5 is a diagram showing the principle of the demultiplexerapparatus of the present invention. With reference to FIG. 5, thedemultiplexer apparatus includes integrating circuits 1 and 2 of twosystems. Each of the integrating circuits adds two-bit data at thetimings shifted for one bit. Consequently, a trinary data, which is anyof 0, 1 and 2, is obtained from each of the integrating circuits 1 and2, on the basis of an input data. Each of the integrating circuitsrecovers an original binary data from this multi-value data.

[0068] This recovering algorism will be described. If the trinary datais 0 or 2, the original binary data can be instantly determined to be0-0 or 1-1. However, if the trinary data is 1, whether the originalbinary data is 0-1 or 1-0 cannot be determined from only the trinarydata. In the present invention, the determination is carried out byreferring to an output data of a different integrating circuit at thistime. In short, if the integration result of the integrating circuititself is 1 and an output of another integrating circuit operatedearlier for one bit of an input data is 0-1 or 1-1, the data read by theintegrating circuit itself can be determined to be 1-0. If the output ofthe other integrating circuit is 1-0 or 0-0, the data read by theintegrating circuit itself is 0-1. In short, an algorism shown in FIG.25 is achieved.

[0069] From the above viewpoint, in the present invention, theintegrating circuits 1 and 2 of the two systems add the two-bit datathat are shifted for the one bit between them, and one of theintegrating circuits 1 and 2 refers to the addition result of the other.Thus, the determination of the data is carried out. In short, if theintegration result or addition result of the integrating circuit 2 is 1and the output of the integrating circuit 1 is 0-0 or 1-0, the output ofthe integrating circuit 2 becomes 0-1. If the output of the integratingcircuit 1 is 0-1 or 1-1, the output of the integrating circuit 2 becomes1-0.

[0070] Consequently, a determination table shown in a table 1 can beprepared as follows. TABLE 1 output of x 0-0 0-1 1-0 1-1 x integratingcircuit 1 integration 0 1 1 1 1 2 value of integrating circuit 2 outputof 0-0 0-1 1-0 0-1 1-0 1-1 integrating circuit 2

[0071] In this way, it could be understood that correct data can berecovered with reference to the opposing data. However, if 1 and 0 arealternately inputted such as 10101010 . . . , this method cannot knowthe first bit of “1” in the input data string. Thus, this method cannotdetermine all of the data after that. Actually, if the data is always10101010 . . . , information can not be transmitted. Therefore, apattern of 00 or 11 appears necessarily. In short, on and after thatpattern, the data can be normally determined.

[0072] In this example, the clock signal used for the integratingcircuit is ¼ of the data rate. Thus, the input data can be processed atthe data rate of four times of the maximum operation frequency of thetransistor to be used.

[0073]FIG. 5 exemplifies the configuration when the data of the two bitsis read at a time. However, in accordance with the principle similar tothe above-mentioned case, the integrating circuits of the n systems (nis an integer of 2 or more) are provided to carry out the integration ofthe input data n bits by n bits at the timings shifted for one bit. Inthis case, each of the integrating circuits can carry out the process atthe data rate of 2n times of the maximum operational frequency. In thisway, in the present invention, since the plurality of data are read inthe one input data reading operation, and the original data can berecovered at the operational frequency lower than the frequencycomponent of the input data.

[0074] Next, FIG. 6 is a block diagram showing the circuit structure ofthe demultiplexer apparatus according to the first embodiment of thepresent invention. With reference to FIG. 6, four integrating circuits10 ₁ to 10 ₄ are provided in parallel. On the input side, the fourintegrating circuits 10 ₁ to 10 ₄ are connected to a common node IN. Theintegrating circuits 10 ₂ to 10 ₄ and 10 ₁ are connected to the outputsof the integrating circuits 10 ₁ to 10 ₄. Consequently, when the timeseries binary data is inputted, the integrating circuit refers to theoutput of the integrating circuit at the previous stage to carry out the1:4 serial-to-parallel conversion. Parallel data D₀ to D₃ are outputtedfrom the integrating circuits 10 ₁ to 10 ₄. It should be noted that thecircuit structure shown in FIG. 6 is only intended to exemplify thepresent invention. In the present invention, the number of integratingcircuits is not limited to 4. FIGS. 7A to 7D are the timing chartsshowing the operation of the demultiplexer apparatus according to thefirst embodiment of the present invention.

[0075] In FIG. 6, clock signals CLK₀ to CLK₃ of four phases are sent tothe integrating circuits 10 ₁ to 10 ₄, respectively, and are differentfrom one another by 90°, as shown in FIGS. 7A to 7D. The integratingcircuits 10 ₁ to 10 ₄ read the time series binary data two bits by twobits. However, the data outputted to the integrating circuit of the poststage operating in the delay of 90°, is only the latter one of the twobits. In short, even if the input IN is 0-1 or 1-1, the output of theintegrating circuit becomes 1. Also, even if the input IN is 1-0 or 0-0,the output of the integrating circuit becomes 0.

[0076] In FIG. 6, only the latter one bit of the two bits is sent to thenext integrating circuit. However, in the present invention, this datais not limited to one bit. Also, in FIG. 6, each integrating circuitreceives the data from only the integrating circuit of an immediatelyfront stage. However, the present invention may be designed such thatthe data can be received from at least one integrating circuit otherthan the integrating circuit of the immediately front stage.

[0077] Next, FIG. 8 is a block diagram showing the circuit structure ofthe integrating circuit 10 for one system shown in FIG. 6. FIGS. 9A to9I are timing charts showing the timings indicative of the operation ofthe integrating circuit 10.

[0078] With reference to FIG. 8, the integrating circuit 10 includes anadding circuit 11, comparing circuits 12-1 and 12-2, latches 13-1 and13-2 of D-type flip-flop, a recovering circuit 14, and a timingadjusting latch 15. The adding circuit 11 adds the input data. Thecomparing circuits 12 (12-1 and 12-2) use a reference voltage H and areference voltage L and classify an addition result A of the addingcircuit 11. The latches 13-1 and 13-2 latch the determined results ofthe comparing circuits 12-1 and 12-2 in synchronism with the clocksignal. The recovering circuit 14 recovers the binary data using anoutput result F of the integrating circuit in the front stage and theoutputs of the latches 13-1 and 13-2. The latch 15 latches the output ofthe recovering circuit 14 to output as an output data.

[0079] The operation of the integrating circuit will be described belowwith reference to FIGS. 9A to 9I.

[0080] As shown in FIG. 9A, in a period while the clock signal is High(a sampling period), the input data for the two bits is integrated bythe adding circuit 11. During a period while the clock signal is Low (aholding period), its data is held. Consequently, a trinary data isoutputted to an output node A of the adding circuit 11 in correspondenceto the two bits of the input data. The trinary data is 2 in case of theinput two bits of 0-0, is 1 in case of the two bits of 0-1, is 1 in caseof the two bits of 1-0, and is 0 in case of the two bits of 1-1. Thetrinary data is indicative of the value added after the two bits of theinput data are inverted.

[0081] The multi-value data as the integration result A in the addingcircuit 11 shown in FIG. 9C is compared with the two reference voltagesHigh and Low by the comparing circuits 12-1 and 12-2, respectively, andtwo binary value data CH and CL are obtained. If a power supply voltageis assumed to be VDD, the reference voltage H is equal to ⅓ of V_(DD),and the reference voltage L is ⅔ of V_(DD). In this way, the referencevoltages are set to be voltages between the trinary data of 0 and 1 andbetween the trinary data of 1 and 2.

[0082] As shown in FIGS. 9D and 9E, the two binary data CH and CL as theoutputs from the comparing circuits 12-1 and 12-2 become CH:CL=1:1, 0:1,0:0, in correspondence to the trinary data of 0, 1 and 2 of theintegration result A. The binary data CH and CL are latched by thelatches 13-1 and 13-2 in synchronization with the input clock signal,and outputted as the outputs H and L from the latches 13-1 and 13-2 tothe recovering circuit 14, as shown in FIGS. 9F and 9G.

[0083] The recovering circuit 14 uses the output H and L from thelatches 13-1 and 13-2 and an output F from the front stage integratingcircuit shown in FIG. 9H, and outputs a result Q shown in FIG. 9I, inaccordance with the following truth table 2. TABLE 2 H 1 0 0 0 L 1 0 1 1F x x 0 1 Q 1 0 1 0

[0084] In FIG. 6, the output timings of the outputs D0 to D3 are notmatched with no control, because the integrating circuits 101 to 104 arerespectively operated in response to the clock signals CLK0 to CLK3whose phases are different from one another. For this reason, in thecircuit structure shown in FIG. 8, the latch 15 in the final stage ofthe integrating circuit is operated so as to adjust the timings of theoutputs by changing a delay time for each integrating circuit. That is,the latch 15 is for a re-timing. It should be noted that in the tables 1and 2, X designates “Don't Care”.

[0085]FIG. 10 is a diagram showing an example of the circuit structureof the adding circuit 11. With reference to FIG. 10, the adding circuit11 has a P-channel MOS transistor M1, an N-channel MOS transistor M2 andan N-channel MOS transistor M3, which are connected in series between apower supply VDD and a ground. A clock signal CLK is commonly inputtedto gates of the MOS transistors M1 and M3, and an input data IN isinputted to a gate of the MOS transistor M2. A variable capacitor C1 isconnected between the ground and a node B as a connection point betweendrains of the MOS transistors M1 and M2. A CMOS transfer switch composedof a P-channel MOS transistor M4 and an N-channel MOS transistor M5 isinserted between the node B and a node A. A complementary signal of theclock signal CLK and the clock signal CLK are inputted to gates of thetransistors M4 and M5, respectively. A capacitor C2 is connected betweenthe node A and the ground.

[0086] In a period while a pulse of the clock signal CLK is High, theN-channel MOS transistor M3 is turned on, and the transfer switchcomposed of the transistors M4 and M5 is turned on. Consequently, onlyduring a period while the input data IN is High, the N-channel MOStransistor M2 is turned on, and charges are discharged from thecapacitors C1 and C2.

[0087] A voltage of the capacitor C2 is held at the node A, since thetransfer switches M4 and M5 are turned off during the period while thepulse of the clock signal CLK is Low. Also, the node B is charged up tothe power supply VDD through the P-channel MOS transistor M1 that isturned on.

[0088] At the timing when a next pulse of the clock signal CLK becomesHigh, the charges in the capacitors C1 and C2 are re-distributed suchthat the voltages of the nodes A and B are equal. In this case, if thecapacitance of the C2 is lower than that of the C1, the change in thevoltage of the node B is smaller than the change in the voltage of thenode A. Here, a time constant of the charging and discharging operationsduring the period while the pulse of the clock signal CLK is High issubstantially determined based on the on-resistances of the N-channelMOS transistors M2 and M3 and the capacitance of the capacitor C1. Thistime constant needs to be changed based on the operational frequency,since the discharging operation must be completed in the time equal to ahalf of the cycle of the clock signal CLK. Thus, the capacitor C is madevariable in order to make the time constant variable as mentioned above.

[0089]FIG. 11 is a diagram showing an example of the circuit structureof the capacitor C1 shown in FIG. 10. With reference to FIG. 11, thevariable capacitor is formed by connecting in parallel, eight MOScapacitors MC0 to MC7, which have different gate capacitances. The MOScapacitor MC_(i) (i=0, 1, 2 to 7) has a high gate capacitance, since achannel is formed only when a control signal CNTi is Low. Thus, thecapacitance value can be accurately controlled through the control ofthe control signals CNT₀ to CNT₇. The data held in an 8-bit register 20on a chip represents the frequency of the clock signal, and the controlsignals CNT₀ to CNT₇ are determined based on the data held by the 8-bitregister 20. Each of the signals obtained by inverting the data held bythe register 20 by inverters INV0 to INV7 is commonly connected to asource and a drain of a corresponding one of the MOS capacitors MC0 toMC7.

[0090]FIGS. 12A to 12C are diagram showing an internal operationalwaveform of the adding circuit 11 in the demultiplexer apparatus in thefirst embodiment. They show the waveforms of the clock signal CLK, theinput data IN and the charging and discharging current of the capacitorC1. By making the waveform of the clock signal CLK close to a sine wavefrom a rectangular wave as shown in FIG. 12A, the charging anddischarging currents during the period while the input data IN is Highare reduced at the first and final parts of the period while the clocksignal CLK is High. Consequently, even if the timings of the signals ofthe clock signal CLK and the signal of the input data IN are shifted,the influence on the output result of the adding circuit is suppressed.In this way, it is possible to increase the operation margin for thetiming shift.

[0091]FIG. 13A is a block diagram showing the circuit structure of thecomparing circuit 12-1 for the reference voltage H. FIG. 13B is a blockdiagram showing the circuit structure of the comparing circuit 12-2 forthe reference voltage L. Consequently, the trinary values of 0, 1 and 2are obtained from the output of the adding circuit 11.

[0092] With reference to FIG. 13A, the comparing circuit 12-1 iscomposed of a constant current source transistor M11 of a P-channel MOStransistor, a differential pair of transistors composed of P-channel MOStransistors M12 and M13, and a differential circuit composed ofN-channel MOS transistors M14 and M15. In the P-channel MOS transistorM11, a source is connected to the power supply V_(DD), and a gate isconnected to the ground. In the differential pair of transistors M12 andM13, sources are commonly connected to a drain of the constant currentsource transistor M11, and gates are connected to a reference voltageREF (the reference voltage H in FIG. 8) and the input data IN,respectively. The N-channel MOS transistors M14 and M15, whichconstitute a current mirror circuit, are connected to drains of thedifferential pair of transistors M12 and M13, respectively. Thus, theyfunction as an active load. An output OUT is taken out from the drain ofthe N-channel MOS transistor M15. When a voltage of the input data IN islower than the reference voltage REF, the output OUT becomes at a Highlevel.

[0093] With reference to FIG. 13B, the comparing circuit 12-2 iscomposed of a constant current source transistor M27 of an N-channel MOStransistor, N-channel MOS transistors M23 and M24 serving as adifferential pair of transistors, and a differential circuit composed ofP-channel MOS transistors M21 and M22. In the constant current sourcetransistor M27, a source is grounded. In the N-channel MOS transistorsM23 and M24, sources are commonly connected to the drain of the constantcurrent source transistor M27, and gates are connected to a referencevoltage REF (the reference voltage L in FIG. 8) and the input data IN,respectively. The P-channel MOS transistors M21 and M22, whichconstitute a current mirror circuit, are connected to drains of thedifferential pair of transistors, respectively. Thus, they function asan active load. An output is taken out from a drain of the P-channel MOStransistor M22. The comparing circuit 12-2 further has a transistor M26,which constitutes the current mirror circuit together with the constantcurrent source transistor M27, and a P-channel MOS transistor M25inserted between a drain of the transistor M26 and the power supply. Agate of the P-channel MOS transistor M25 is grounded. The constantcurrent source transistor M27 drives the differential pair oftransistors M23 and M24 through a mirror current as a drain current ofthe P-channel MOS transistor M25. When a voltage of the input data IN islower than the reference voltage REF, the output OUT becomes at a Highlevel.

[0094]FIGS. 14A and 14B are circuit diagrams showing the circuitstructure of the recovering circuit 14 in the demultiplexer apparatus ofthe first embodiment. The recovering circuit 14 attains the truth tableshown in the table 2. The recovering circuit 14 uses different circuitsto even-numbered bits D0 and D2 and odd-numbered bits D1 and D3. Withreference to FIG. 14A, the circuit portion of the recovering circuit forthe even-numbered bits is composed of a NAND circuit NAND1 for receivingan inversion signal of the output F from the previous stage integratingcircuit and the output L of the latch 13-2, and a NAND circuit NAND2 forreceiving an output of the NAND1 and a signal obtained by inverting theoutput H from the latch 13-1 by the inverter INV11.

[0095] Also, with reference to FIG. 14B, the circuit portion of therecovering circuit for the odd-numbered bits is composed of a NORcircuit NOR1 for receiving the output F from the previous stageintegrating circuit and a signal obtained by inverting the output L fromthe latch 13-2 by the inverter INV12, and a NOR circuit NOR2 forreceiving an output of the NOR1 and the output H from the latch 13-1.

[0096] The integrating circuits 101 to 104 for the bits D0 to D3 areoperated at the phases shifted by the quarter clock signal (90°) fromone another. Thus, the time from the input of the output F from theprevious stage integrating circuit to the output of the output data Qneeds to be equal to or less than the period of the quarter clocksignal. For this reason, the optimization of the logic is carried out inorder to reduce the number of gate stages in the integrating circuit, asshown in FIGS. 14A and 14B. As a result, the different circuits are usedfor the even-number bits and the odd-numbered bits.

[0097]FIG. 15 is a circuit diagram showing another circuit structureexample of the recovering circuit 14 used in the demultiplexer apparatusof the first embodiment. In this circuit structure example, the samecircuits are used for the even-numbered and odd-numbered bits. Therecovering circuit 14 is composed of P-channel MOS transistors M31 andM32, N-channel MOS transistors M33 and M34 and inverters INV21 andINV22. The transistors M31 to M34 are connected in series between thepower supply and the ground. A signal obtained by inverting the output Lby the inverter INV21 is sent to a gate of the transistor M31, and theoutput F is sent to gates of the transistors M32 and M33. A signalobtained by inverting the output H by the inverter INV22 is sent to agate of the transistor M34. The above-mentioned circuit structureexample is further composed of a P-channel MOS transistor M35 and anN-channel MOS transistor M36, which are connected in series between thepower supply and the ground. A signal obtained by inverting the output Hby the inverter INV22 is sent to a gate of the transistor M35, and asignal obtained by inverting the output L by the inverter INV21 is sentto a gate of the transistor M36. A connection point between drains ofthe P-channel MOS transistor M32 and the N-channel MOS transistor M33 isconnected to a connection point between drains of the P-channel MOStransistor M35 and the N-channel MOS transistor M36, and an output Q isoutputted from that connection point. The output Q is outputted as anoutput F to a next stage.

[0098] As mentioned above, the demultiplexer apparatus in the firstembodiment of the present invention has the first to N-th integratingcircuits which commonly receive the input binary data. The first to N-thintegrating circuits are driven on the basis of the first to N-th clockswhose phases are different from one another. Also, the (i+1)-th (i=apositive integer from 1 to N−1) integrating circuit refers to the i-thintegrating circuit that is the integrating circuit in the previousstage of the integrating circuit (However, if i=N, the (N+1)-thintegrating circuit becomes the first integrating circuit, and the firstintegrating circuit refers to the output of the N-th integratingcircuit). The (i+1)-th integrating circuit may refer to the integratingcircuits at the previous stage of the (i+1)-th integrating circuit,namely, the integrating circuits before the i-th integrating circuit,namely, the (i−1)-th, (i−2)-th . . . , integrating circuits other thanthe i-th integrating circuit. The phase of the clock sent to thisintegrating circuit is delayed for one bit data than that of the clocksent to the integrating circuit at the previous stage of the (i+1)-thintegrating circuit. Each of the integrating circuits has an addingcircuit 11 for adding the input binary data in a plurality of bits. Thecomparing circuit 12 compares the multi-value data as the added resultby the adding circuit 11 with the reference voltage, and generates aplurality of binary data. The recovering circuit 14 recovers theoriginal binary data from the plurality of binary data outputted by thecomparing circuit 12 and the output result F of the previous stageintegrating circuit. The output from the recovering circuit 14 islatched by the latch 15 and then outputted after the timing is adjusted.

[0099] Next, the integrating circuit according to the second embodimentof the present invention will be described below. FIG. 16 is a diagramshowing the circuit structure of the integrating circuit according tothe second embodiment of the present invention. With reference to FIG.16, the integrating circuit in the second embodiment is composed of twoadding circuits, namely, plus and negative adding circuits 41-1, 41-2.The positive adding circuit 41-1 adds the input signals and generatesthe multi-value data of 0, 1 and 2. The negative adding circuit 41-2adds the input signals and generates the multi-value data of thepolarity opposite to the addition result of the positive adding circuit41-1. In the multi-value data of the opposite polarity, 0 of the pluspolarity corresponds to 2, and 2 of the plus polarity corresponds to 0.The multi-value data output from the positive and negative addingcircuits 41-1 and 41-2 obtained as mentioned above are as illustrated inthe following table 3. TABLE 3 input data 0-0 0-1 1-0 1-1 positiveadding 0 1 1 2 circuit negative adding 2 1 1 0 circuit

[0100] The multi-value data of the addition result is any of the trinarydata of 0, 1 and 2. This trinary data is compared with one referencevoltage set to the voltage between 1 and 0. Then, the binary data isobtained from the two comparing circuits 42-1 and 42-2. The followingtable 4 illustrates and lists the outputs of the plus comparing circuitand the minus comparing circuit in this embodiment. TABLE 4 input data0-0 0-1 1-0 1-1 plus comparing 0 1 1 1 circuit minus comparing 1 1 1 0circuit

[0101] Though the use of the output of this comparing circuit and theoutput of the integrating circuit of the previous stage, the data can berecovered as illustrated in the following table 5. TABLE 5 output ofpre-stage x x 0 1 integrating circuit (FT) plus output of plus 0 1 1 1comparing circuit (TT) minus output of minus 1 0 1 1 comparing circuit(TT) recovered data (OUT) 0 1 1 0

[0102]FIG. 17 is a diagram showing an example of the circuit structureof a recovering circuit 44 to attain the determination table in thetable 5. The recovering circuit 44 is composed of a differential pair oftransistors M43 and M44 composed of N-channel MOS transistors, P-channelMOS transistors M41 and M42, an N-channel MOS transistor M45, anN-channel MOS transistor M46, a differential pair of transistors M47 andM48 composed of N-channel MOS transistors, and a constant current sourcetransistor M49 composed of an N-channel MOS transistor. In thedifferential pair of transistors M43 and M44, sources are commonlyconnected, and complementary output signals FB and FT of the previousstage integrating circuit are sent to the gates. The P-channel MOStransistors M41 and M42 constitute the active loads of the differentialpair of transistors M43 and M44. In the N-channel MOS transistor M45, adrain is connected to the common source of the differential pair oftransistors M43 and M44, and a plus output TT of the plus comparingcircuit is connected to a gate. In the N-channel MOS transistor M46, adrain is connected to a source of the transistor M45, and a plus outputBT of the minus comparing circuit is connected to a gate. In thedifferential pair of transistors M47 and M48, drains are connected tothe drains of the differential pair of transistors M43 and M44,respectively, and sources are commonly connected, and a minus output TBof the plus comparing circuit and a minus output BB of the minuscomparing circuit are connected to gates, respectively. In the constantcurrent source transistor M49, a drain is connected to the source of thetransistor M46 and the common source of the differential pair oftransistors M47 and M48, and a source is grounded. The recoveringcircuit 44 is further composed of an N-channel MOS transistor M51 and aP-channel MOS transistor M50 provided between a drain of the transistorM51 and the power supply. A gate of the P-channel MOS transistor M50 anda source of the N-channel MOS transistor M51 are grounded. A gate of theconstant current source transistor M49 is connected to a gate and adrain of the N-channel MOS transistor M51. Thus, the transistor M49constitutes a current mirror circuit together with the N-channel MOStransistor M51. The transistors M43, M44, M45, M46, M47 and M48 aredriven by the mirror current of the drain current of the P-channel MOStransistor M50.

[0103]FIG. 18 is a diagram showing the circuit structure of ademultiplexer apparatus according to the third embodiment of the presentinvention. With reference to FIG. 18, two recovering circuits 14-1 and14-2 are provided for a one-system integrating circuit. The recoveringcircuits 14-1 and 14-2 recover the data under the presumption that theoutput F at the previous stage integrating circuit is 0 or 1. Then, atthe time when the output of the previous stage integrating circuit isactually determined, a selecting circuit 17 selects an output of therecovering circuit 14-1 if the output of the previous stage integratingcircuit is 0, and outputs the recovery data. If the output of theprevious stage integrating circuit is 1, the selecting circuit 17selects an output of the recovering circuit 14-2 and outputs therecovery data Q. Consequently, it is possible to shorten the time fromthe determination of the output of the previous stage integratingcircuit to the determination of the self-output. Also, the recovery dataQ is sent as the output F to an integrating circuit at a next stage.

[0104]FIG. 19 is a diagram showing the circuit structure of ademultiplexer apparatus according to the fourth embodiment of thepresent invention. With reference to FIG. 19, in an integrating circuitin the fourth embodiment, n recovering circuits 14 ₁ to 14 _(n) areprovided for a one-system integrating circuit. The recovering circuit tobe used is switched in turn by a switch SW1, for each adding operationin the integrating circuit. Consequently, a period in which onerecovering circuit can be used to recover the data is made longer to atime corresponding to n adding operations. Thus, a margin can be givento the timing of the recovering circuit. Also, one of outputs from the nrecovering circuits 14 ₁ to 14 _(n) is selected by a switch SW2 andoutputted as an output Q.

[0105]FIG. 20 is a diagram showing the circuit structure of ademultiplexer apparatus according to the fifth embodiment of the presentinvention. With reference to FIG. 20, the demultiplexer apparatus in thefifth embodiment is composed of binary to multi-value data converters 18₁ to 18 ₂ for converting the input binary data into the multi-valuedata, signal amplifiers 19 ₁ to 19 _(n) for amplifying the outputs ofthe binary to multi-value data converters 18 ₁ to 18 ₂, and a recoveringcircuit 14 for recovering the binary data from outputs of the signalamplifiers 19 ₁ to 19 _(n). If the data recovery is performed on a smallinput signal, at first, the conversion into the multi-value data iscarried out at a stage of the small input signal, as shown in FIG. 20.The generated multi-value data has only frequency components equal to orless than a half of the input binary data. Thus, the frequency bandnecessary for the following amplifiers 19 ₁ to 19 _(n) and the like canbe made narrower. In this embodiment, the circuit for referring to thedifferent integrating circuits is assembled in the recovering circuit14.

[0106]FIG. 21 is a diagram showing the circuit structure of ademultiplexer apparatus according to the sixth embodiment of the presentinvention. With reference to FIG. 21, an integrating circuit in thesixth embodiment is composed of n sub-integrating circuits 30 ₁ to 30_(n) and a selecting circuit 31 for selecting and outputting one of theoutputs of the respective sub-integrating circuits. Each of thesub-integrating circuits has the circuit structure similar to theintegrating circuit shown in FIG. 6, and is compose of the addingcircuit, the comparing circuit, the recovering circuit and the like.

[0107]FIGS. 22A to 22D are timing charts showing the timings in theoperation of the demultiplexer apparatus in the sixth embodiment shownin FIG. 21 of the present invention.

[0108] With reference to FIG. 18, the n timing signals are generatedfrom the clock signals inputted to the integrating circuits of FIG. 21,and a sampling period is allocated to a different sub-integratingcircuit for every sampling time. At this time, the other (n−1)sub-integrating circuits to which the sampling period is not allocatedare at the holding period in which the input data is held and recovered.The selecting circuit 31 selects and outputs only one from the outputsof the sub-integrating circuits. Thus, the sub-integrating circuit canhave the holding period longer the sampling time. Therefore, the longtime can be used for recovering the input data so that the margin can begiven to the timing.

[0109]FIG. 23 is a diagram showing the circuit structure of thedemultiplexer apparatus according to the sixth embodiment of the presentinvention. With reference to FIG. 23, the integrating circuit also has nsub-integrating circuits 32 ₁ to 32 _(n) similarly to the integratingcircuit of FIG. 21. The outputs of the respective sub-integratingcircuits are outputted in their original states to the external portionof the integrating circuit. Thus, one integrating circuit carries outthe 1:n serial-to-parallel conversion. Therefore, if there are mintegrating circuits, the 1:n×m serial-to-parallel conversions can becarried out in the entire circuit.

[0110] As mentioned above, the present invention has been described withreference to the above-mentioned embodiments. However, the presentinvention is not limited to the circuit structures of theabove-mentioned embodiments. Various modifications that may be attainedby one skilled in the art are included the scope of the presentinvention.

[0111] As explained above, according to the present invention, the inputbinary data is converted into the multi-value data having the lowerfrequency components. Thus, it is possible to process the input dataexceeding the maximum operational frequency of the transistorsconstituting the circuit.

1. A demultiplexer apparatus comprising a plurality of integratingcircuits which operate in parallel, wherein said plurality ofintegrating circuits receive in parallel an input time-series binarydata, each of the plurality of integrating circuits in a current stageconverts said input binary data into multi-value data in said currentstage, and generates recovery data in said current stage based on saidmulti-value data in said current stage and recovery data from one ofsaid plurality of integrating circuits in a stage immediately or moreprevious to said integrating circuit in said current stage, and saidplurality of integrating circuits output the generated recovery data asparallel data to said input binary data.
 2. The demultiplexer apparatusaccording to claim 1, wherein each of said plurality of integratingcircuits generates said recovery data in said current stage integratingcircuit based on said multi-value data in said current stage and saidrecovery data from said immediately previous integrating circuit to saidcurrent stage integrating circuit, and outputs the generated recoverydata to one of said plurality of integrating circuits in a next stage.3. The demultiplexer apparatus according to claim 1 or 2, wherein eachof said plurality of integrating circuits operates at a timing shiftedfor one data quantity of said input binary data from an operation timingof said immediately previous stage integrating circuit.
 4. Thedemultiplexer apparatus according to any of claims 1 to 3, wherein eachof said plurality of integrating circuits comprises: a converting unitwhich converts said input binary data into the multi-value data forevery data quantities of a predetermined number.
 5. The demultiplexerapparatus according to claim 4, wherein said converting unit adds saidinput binary data for every n data quantities (n is an integer of 1 ormore) to generate the multi-value data.
 6. The demultiplexer apparatusaccording to claim 4 or 5, wherein said converting unit comprises anadding circuit, wherein said adding circuit comprises: a capacitor; anda switch, and said switch operates in response to a clock signal tocarry out addition such that a charge is stored in said capacitor andthen the stored charge is discharged from said capacitor based on saidinput binary data, or such that the charge is discharged from saidcapacitor and then said capacitor is charged based on said input binarydata.
 7. The demultiplexer apparatus according to claim 6, wherein saidadding circuit further comprises: a transfer gate connected to saidcapacitor; and an output capacitor connected through said transfer gateto said capacitor, a capacitance of said output capacitor is smallerthan that of said capacitor.
 8. The demultiplexer apparatus according toclaim 6 or 7, wherein the capacitance of said capacitor is variablebased on a period per each data quantity of said input binary data. 9.The demultiplexer apparatus according to claim 8, wherein said capacitorcomprises: a plurality of MOSFETs whose gate electrodes are connected inparallel, and the capacitance of said capacitor is adjusted by formingor extinguishing a gate channel of each of said plurality of MOSFETsbased on the period per each data quantity of said input binary data.10. The demultiplexer apparatus according to claim 8 or 9, wherein awaveform of the clock signal is determined such that current valuesassociated with said capacitor in head and final portions in a period ofthe addition are smaller than a current value during a portion betweenthe first and final portions in the period of the addition.
 11. Thedemultiplexer apparatus according to any of claims 4 to 10, wherein eachof said plurality of integrating circuits further comprises: a pluralityof comparing circuits which converts said multi-value data into a set ofbinary data, and different thresholds are allocated to said plurality ofcomparing circuits, respectively.
 12. The demultiplexer apparatusaccording to claim 11, wherein each of said plurality of integratingcircuits further comprises: a recovering unit which generates saidrecovery data in said current stage based on the set of binary data andsaid recovery data from said immediately previous stage integratingcircuit.
 13. The demultiplexer apparatus according to any of claims 1 to11, wherein each of said plurality of integrating circuits furthercomprises: a plurality of recovering circuits provided for recovery dataestimations from said immediately previous stage integrating circuit,wherein each of said plurality of recovering circuits generates saidrecovery data estimation based on the set of binary data and acorresponding one of the recovery data estimations; and a selectingcircuit which selects one of said recovery data estimations fromplurality of recovery data based on said recovery data from saidimmediately previous stage integrating circuit, and outputs as saidrecovery data of said current stage integrating circuit.
 14. Thedemultiplexer apparatus according to any of claims 1 to 11, wherein eachof said plurality of integrating circuits comprises: a plurality ofrecovering circuits, each of which generates said recovery data in saidcurrent stage integrating circuit based on the set of binary data andsaid recovery data of said immediately previous stage integratingcircuit; a first switch which sequentially selects one of said pluralityof recovering circuits and sends the set of binary data to the selectedrecovering circuit; and a second switch which selects one of saidplurality of recovering circuits and outputs said recovery data in saidcurrent stage from the selected recovering circuit.
 15. Thedemultiplexer apparatus according to any of claims 12 to 14, whereineach of said plurality of integrating circuits comprises: a latchingcircuit which adjusts timings such that the generated recovery data aresimultaneously outputted as said parallel data to said input binarydata.
 16. The demultiplexer apparatus according to any of claims 1 to15, wherein said demultiplexer apparatus comprises a plurality ofintegrating units, and each of said plurality of integrating unitscomprises: said plurality of integrating circuits.
 17. The demultiplexerapparatus according to any of claims 1 to 11, wherein said demultiplexerapparatus comprises a plurality of integrating units, each of saidplurality of integrating units comprising said plurality of integratingcircuits; and a selector which selects one of said plurality ofintegrating units and outputs an output data from the selectedintegrating unit as said parallel data.
 18. The demultiplexer apparatusaccording to claim 17, wherein each of said plurality of integratingcircuits comprises: a latching circuit which adjusts a timing such thatthe generated recovery data are simultaneously outputted as saidparallel data to said input binary data.
 19. The demultiplexer apparatusaccording to any of claims 1 to 3, wherein each of said plurality ofintegrating circuits comprises: a first converting unit which generatesfirst multi-value data from said input binary data for eachpredetermined data quantity; and a second converting unit whichgenerates second multi-value data from said input binary data for eachpredetermined data quantity, said multi-value data contains the firstmulti-value data and the second multi-value data, and the secondmulti-value data contains data of a polarity opposite to that of thefirst multi-value data.
 20. The demultiplexer apparatus according toclaim 19, wherein each of said first and second converting units addssaid input binary data for every n data (n is an integer of 1 or more)and generates the multi-value data.
 21. The demultiplexer apparatusaccording to claim 19 or 20, wherein each of said first and secondconverting units comprises an adding circuit, said adding circuitcomprises: a capacitor; and a switch, said switch operates in responseto a clock signal to carry out addition such a charge is stored in thecapacitor and then the stored charge is discharged from said capacitorbased on said input binary data, or such that the stored charge isdischarged, and then said capacitor is charged based on said inputbinary data.
 22. The demultiplexer apparatus according to claim 21,wherein said adding circuit further comprises: a transfer gate connectedto said capacitor; and an output capacitor connected through saidtransfer gate to said capacitor, and a capacitance of said outputcapacitor is smaller than that of said capacitor.
 23. The demultiplexerapparatus according to claim 21 or 22, wherein the capacitance of saidcapacitor is variable based on a period per data of said input binarydata.
 24. The demultiplexer apparatus according to claim 23, whereinsaid capacitor comprises: a plurality of MOSFETs whose gate electrodesare connected in parallel, and the capacitance of said capacitor isadjusted by forming or extinguishing a channel of each of said pluralityof MOSFETs based on the period per data of said input binary data. 25.The demultiplexer apparatus according to claim 23 or 24, wherein awaveform of the clock signal is determined such that current valuesthrough the stored charge at first and final portions in the additionare smaller than that in a period between the first and final portionsin the addition.
 26. The demultiplexer apparatus according to any ofclaims 19 to 25, wherein each of said plurality of integrating circuitsare provided for said fist and second converting units, and comprises: aplurality of comparing circuits which convert the multi-value data intoa set of binary data, and same thresholds are allocated to saidplurality of comparing circuits.
 27. The demultiplexer apparatusaccording to claim 26, wherein each of said plurality of integratingcircuits further comprises: a recovering circuit which generates saidrecovery data in said current stage integrating circuit based on the setof binary data and said recovery data from said immediately previousstage integrating circuit.
 28. The demultiplexer apparatus according toany of claims 19 to 27, wherein each of said plurality of integratingcircuits comprises: a latching circuit which adjusts a timing such thatthe generated recovery data are simultaneously outputted as saidparallel data to said input binary data.
 29. A communication apparatuscomprising: said demultiplexer apparatus according to any of claims 1 to28.
 30. A demultiplexer apparatus comprising: first to N-th integratingcircuits (N is an integer of two or more) operating in parallel, whichcommonly receive a serial binary data, wherein said first to N-thintegrating circuits operate in response to first to N-th clock signalswhose phases are different from one another, each of said integratingcircuits refers to an output of one of said integrating circuits in animmediately previous stage, one of said integrating circuits in a firststage refers to an output of said N-th integrating circuit, and each ofthe integrating circuits comprises: an adding circuit which adds saidserial binary data for a plurality of bits; a comparing circuit whichcompares multi-value data obtained by the addition by said addingcircuit with a reference voltage and generates a plurality of binarydata; and a recovering unit which recovers parallel binary data fromsaid plurality of binary data outputted from said comparing circuit andan output of said immediately previous stage integrating circuit, andoutputs at least a part of the recovered parallel binary data to one ofsaid integrating circuits in a next stage.
 31. The demultiplexerapparatus according to claim 30, wherein said adding circuit comprises:a first conductive type of a first MOS transistor, a second conductivetype of a second MOS transistor, and the second conductive type of athird MOS transistor, wherein said first to third MOS transistors areconnected in series between a high potential side power supply and a lowpotential side power supply, a clock signal to be supplied to theintegrating circuit is supplied to gates of said first and third MOStransistors, said serial binary data is supplied to a gate of saidsecond MOS transistor; a first capacitor, whose one end is connected toa connection point between drains of said first MOS transistor and saidsecond MOS transistor, and the other end is connected to the low or highpotential side power supply, and a capacitance is variable; a transferswitch, which is connected between the one end of said first capacitorand the output end of said adding circuit and controlled to be turned onand off by the clock signal; and a second capacitor in which one end isconnected to a connection point between said transfer switch and theoutput end, and the other end is connected to the low or high potentialside power supply, and a capacitance of said second capacitor is smallerthan that of said first capacitor.
 32. The demultiplexer apparatusaccording to claim 31, wherein said transfer switch is set to an onstate when said third MOS transistor whose gate receives the clocksignal is in the on state, and is set to an off state when said thirdMOS transistor is in an off state.
 33. The demultiplexer apparatusaccording to claim 32 or 33, wherein said transfer switch is turned offto disconnect said second capacity from said first capacity when saidaddition using said first capacity is ended, then said first capacity isdischarged or charged, to return to a state before said addition, atstart of a next addition, said transfer switch is turned on to set saidsecond capacity and said first capacity to a same voltage.
 34. Thedemultiplexer apparatus according to any of claims 30 to 33, whereinsaid integrating circuit further comprises: a latching circuit whichreceives an output from said recovering unit, and adjusts a timing andoutputs as the output data.
 35. The demultiplexer apparatus according toany of claims 30 to 34, wherein the clock signal supplied to saidintegrating circuit has its phase which is delayed for one bit, ascompared with the clock signal supplied to said immediately previousstage integrating circuit.
 36. The demultiplexer apparatus according toany of claims 30 to 35, wherein said recovering unit comprises: acircuit which recovers even-numbered bits; and a circuit which recoversodd-numbered bits.
 37. A communication apparatus comprising saiddemultiplexer apparatus according to any of claims 30 to 36.